Publications:Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support

From CERES
Jump to: navigation, search

Do not edit this section

Keep all hand-made modifications below

Title Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support
Author Kristina Kunert and Mattias Weckstén and Magnus Jonsson
Year 2007
PublicationType Conference Paper
Journal
HostPublication Proceedings of the 2nd international conference on Nano-Networks
DOI
Conference Nanonet07 Second International Conference on Nano-NetworksCatania, Italy, September 24 - 26, 2007
Diva url http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:239443
Abstract Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks and in order to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this paper, we present an algorithm for the choice of topology in, e.g., on-chip networks, considering realtime demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures.