Publications:Formal analysis of non-determinism in Verilog cell library simulation models

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Title Formal analysis of non-determinism in Verilog cell library simulation models
Author Matthias Raffelsieper and Mohammad Reza Mousavi and Jan-Willem Roorda and Chris Strolenberg and Hans Zantema
Year 2009
PublicationType Conference Paper
Journal
HostPublication Formal Methods for Industrial Critical Systems : 14th International Workshop, FMICS 2009, Eindhoven, The Netherlands, November 2-3, 2009. Proceedings
DOI http://dx.doi.org/10.1007/978-3-642-04570-7_11
Conference 14th International Workshop on Formal Methods for Industrial Critical Systems, Eindhoven, NETHERLANDS, NOV 02-03, 2009
Diva url http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:584506
Abstract Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve non-determinism, which in turn, poses a challenge to their validation. Simulators often resolve such problems by using certain rules to make the specification deterministic. This however is not justified by the behavior of the hardware that is to be modeled. Hence, simulation might not be able to detect certain errors. In this paper we develop a technique to prove whether non-determinism does not affect the behavior of the simulation model, or whether there exists a situation in which the simulation model might produce different results. To make our technique efficient, we show that the global property of equal behavior for all possible evaluations is equivalent to checking only a certain local property.