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Publications:A Study of Design Efficiency with a High-Level Language for FPGAs
Abstract <p>Over the years reconfigurable com<p>Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used for mapping computations to such architectures still require the knowledge about architectural details of the target device to extract efficiency. A study of the Mobius language and tools is presented in this paper, with a focus on generated hardware performance. A number of streaming and memory-intensive applications have been developed and the results have been compared with the corresponding implementations in VHDL and a behavioral hardware description language. Based upon experimental evidences, it is concluded that Mobius, a minimal parallel processing language targeted for reconfigurable architectures, enhances productivity in terms of design time and code maintainability without considerably compromising performance and resources.</p>ising performance and resources.</p>
Author Zain Ul-Abdin + , Bertil Svensson +
Conference 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, 26 - 30 March, 2007
DOI http://dx.doi.org/10.1109/IPDPS.2007.370394  +
Diva http://hh.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:239186
EndPage 7  +
HostPublication Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Abstracts and CD-ROM  +
PublicationType Conference Paper  +
Publisher IEEE Press  +
StartPage 1  +
Title A Study of Design Efficiency with a High-Level Language for FPGAs  +
Year 2007  +
Has queryThis property is a special property in this wiki. Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs + , Publications:A Study of Design Efficiency with a High-Level Language for FPGAs +
Categories Publication  +
Modification dateThis property is a special property in this wiki. 26 June 2014 03:41:37  +
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